1. Field of the Invention
The present invention relates to a laterally diffused metal-oxide-semiconductor (LDMOS) device and, more particularly, to a LDMOS device with a reduced hot carrier injection effect.
2. Description of the Prior Art
Power MOS devices, including laterally diffused metal-oxide-semiconductor (LDMOS) devices, are employed in a variety of applications, such as, for example, power amplifiers in wireless communications systems. Especially, LDMOS device using Vg, (gate voltage)=5V seems to become a main stream in the application. The Vd, (drain voltage) of such LDMOS may be a various voltage depending on device's application.
FIG. 1 schematically illustrates a cross-sectional view of a conventional laterally diffused NMOS device. The conventional laterally diffused NMOS device 1 is fabricated on an active area of a semiconductor substrate 10 such as a P-type semiconductor substrate. The active area is isolated by a peripheral field oxide layer 12. Generally, the NMOS device 1 comprises a source doping region 14, a gate 16 and a drain doping region 18. The source doping region 14 is a heavily N-doped region bordering a heavily P-doped region 20, both of which are formed within a P-body region 22. The distance between the drain doping region 18 and the source doping region 14 may be a few micrometers. The drain doping region 18 is a heavily N-doped drain. A gate dielectric layer 24 is formed beneath the gate 16. The gate 16 is formed on the gate dielectric layer 24 and laterally extends over a field oxide layer 26. The field oxide layer 26 is formed in a N-doped drift region 28 between drain diffusion and channel diffusion using a local oxidation of silicon (LOCOS) technique. To prevent breakdown of the MOS device operated at a high voltage, the field oxide layer 26 requires a certain thickness. The P-body region 22, the drift region 28, and the drain doping region 18 are all formed within a deep N-well 30 in the semiconductor substrate 10.
However, in the conventional LDMOS, since the thickness of the gate dielectric layer (gate oxide) on the channel diffusion always keeps the same in the whole, a trade off phenomenon is faced:
1. In order to lower Vt, (threshold voltage) of LDMOS or increase Idlin, (linear drive current), a thin gate dielectric layer is preferred in the channel region.
2. Following the term 1,, a serious hot carrier injection (HCI) issue will occur, leading the device to burn out in advance.
HCl in an MOS device generally results from heating and subsequent injection of carriers into the gate oxide of the device, which results in a localized and non-uniform buildup of interface states and oxide charges near and underneath a gate of the device. As is well known in the art, the buildup of interface states, which are typically defined as trapped charges in an interface between an upper surface of the semiconductor substrate and an oxide layer formed on the substrate, generally results from a high electric field distribution proximate the silicon/oxide interface. This phenomenon can produce variations in certain characteristics of the MOS device, including threshold voltage, transconductance, drain current, etc., thus undesirably affecting the performance and reliability of the device. It is well known that HCI is a strong function of the internal electric field distributions at the silicon/oxide interface of the MOS device.
Currently, an increased field oxidation layer (FOX) width or an offset of drain side to the gate is used in order to decrease hot carrier injection issue, thus the device pitch is enlarged and Idlin, performance is deteriorated, and finally a high Rdson, (drain-source on-state resistance) is caused, and the performance and reliability of the device are undesirably affected.
Therefore, there is still a need for an improved LDMOS structure and the manufacturing method to reduce the hot carrier effect.